Semiconductor manufacturing is a process of forming a stacked structure on a substrate by a variety of processes such as photolithography, etching, deposition, and implantation, etc. The correlation between different material layers in the stacked structure easily affects the performance of the semiconductor device.
To improve the performance of the semiconductor device, each patterned material layer needs to be aligned with the previously patterned material layer during the semiconductor manufacturing process. In other words, the semiconductor process needs to meet a certain overlay accuracy. If an alignment error is large, the performance of the semiconductor device is affected, and short circuit and/or device failure issues caused by misalignment of connection layers may even occur.
A photolithography technology is often used to transfer pattern on a mask to a wafer in the semiconductor manufacturing process. Therefore, the alignment of the mask to the wafer during the photolithography process is directly related to the alignment of the material layers in the wafer. Reducing the alignment error between the wafer and the mask can effectively improve the accuracy of the pattern provided in the material layer, and the alignment accuracy between the different patterned material layers.
However, the alignment method used in the existing photolithography process has a large alignment error issue. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.